1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, e.g., an ESD protection circuit for protecting a semiconductor device from an overcurrent such as a surge that may be applied to the semiconductor device.
2. Description of the Related Art
An ESD protection circuit for protecting an internal circuit from an overcurrent applied to a pad is usually formed in an I/O portion of a semiconductor device such as a large-scale integrated circuit (LSI). This protection circuit is formed for each input pin, an output pin, and a power supply pin of a semiconductor device.
An example of a protection circuit connected to an input pin will be explained below. The protection circuit includes, e.g., an input pad, two diodes, an input buffer, and an inter-power supply protection element. The two diodes are connected in series. This series-connected structure has an anode connected to a common potential (ground potential or reference potential (VSS)) line, and a cathode connected to a power supply potential (VDD) line. The input buffer comprises n- and p-type metal oxide semiconductor field effect transistors (MOSFETs) connected in series. That is, one terminal (drain terminal) of the n-type MOSFET and one terminal (drain terminal) of the p-type MOSFET are connected, the other terminal (source terminal) of the n-type MOSFET is connected to the common potential line, and the other terminal (source terminal) of the p-type MOSFET is connected to the power supply potential line. The input pad is connected to the gate terminals of the two MOSFETs. The inter-power supply protection element is connected between the power supply potential line and common potential line. The inter-power supply protection element holds the potential difference between the power supply potential line and common potential line constant.
When a surge current having a positive potential with respect to the common potential is input to the input pad, for example, the potential of the input pad rises. Then, the potential of the power supply potential line connected to the input terminal via the diodes also rises. Accordingly, the inter-power supply protection element operates to hold the potential difference between the power supply potential line and common potential line at a constant value by discharging the surge current. After the protection circuit thus operates, it is possible to prevent electrostatic destruction of a circuit formed between the power supply potential line and common potential line by holding the potential difference between the input pad and common potential line constant.
If, however, the response speed of the inter-power supply protection element to the surge current is not sufficiently higher than the rising speed of the surge current, it is sometimes impossible to protect the circuit. In this case, the inter-power supply protection element cannot discharge the surge current applied to the input pad, and the potential of the common potential line rises. Consequently, a high voltage is applied between the source and gate terminals of the n-type MOSFET. If this potential difference exceeds a breakdown voltage corresponding to the characteristics of the n-type MOSFET, the n-type MOSFET is destroyed. When a negative potential based on the common potential is applied to the input pad, the same mechanism as described above may destroy the p-type MOSFET.
This problem is highly likely to become serious in the implementation of a protection circuit to be adapted to a test method called a charged device model (CDM). The CDM is a kind of a test method, and one feature of this method is that a steep surge current flows.
As an example of prior art references relevant to the invention of this application, Jpn. Pat. Appln. KOKAI Publication No. 08-275375 describes an electrostatic discharge protection circuit in which a single transistor is connected between circuit nodes of a Vcc pin and Vss pin.